Electro-optical device and driving method for the same

ABSTRACT

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     A grey tone display and a driving method are described. The display comprises a light influencing layer, an electrode pad located adjacent to the layer at one side of the layer in order to define a pixel in the layer, an n-channel field effect transistors connected to the electrode pad at its source terminal, a p-channel field effect transistors connected to the electrode pad at its source terminal, a first control line connected to the drain terminal of the n-channel field effect transistor, a second control line connected to the drain terminal of the p-channel field effect transistor, a third control line connected to the gate terminals of the n-channel field effect transistor and the p-channel field effect transistor, and a control circuit for supplying control signals to the first, second and third control lines. By this configuration, the voltage of the electrode pad can be arbitrarily controlled by adjusting the input level at the gate terminals.

This is a Divisional application of Ser. No. 08/766,709, filed Dec. 13,1996, which is a Divisional application of Ser. No. 08/542,821, filedOct. 13, 1995, now U.S. Pat. No. 5,612,799; which is a Divisionalapplication of Ser. No. 08/224,992 filed Apr. 8, 1994, now U.S. Pat. No.5,495,353; which is a Divisional application of Ser. No. 07/673,458filed Mar. 22, 1991, now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a grey tone display and a drivingmethod for the same and, more particularly to a display driving systemutilizing complimentary thin film gate insulated field effecttransistors suitable for used in liquid crystal displays.

2. Description of the Prior Art

There have been well known in the art active liquid crystal displayswhich are driven by thin film transistors (TFTs) The displays of thistype comprise visual panels and peripheral circuits for driving thepanel. The peripheral circuit is formed by attaching a singlecrystalline chip containing integrated circuits on a glass substrate bytab-bonding or COG (chip on glass). The visual panel comprises aplurality of pixels each being provided with a driving TFT. The TFT isusually an N-channel FET formed within an amorphous or polycrystallinesemiconductor film which is electrically coupled to a respective pixel.

FIG. 1 is a diagram illustrating the equivalent circuit of an exemplaryliquid crystal display. The diagram shows only a 2×2 matrix for the sakeof convenience in description whereas ordinary liquid crystal displaysconsist of more great numbers of pixels such as those in the form of a640×480 matrix, a 1260×960 matrix and so on. The liquid crystal displayincludes a liquid crystal layer 42 disposed between a pair of glasssubstrates 11 and 11' as shown in FIG. 2. Numeral 54 designates apolarizing plate. The inner surface of the glass substrate 11' is coatedwith a ground electrode 53. The inner surface of the other substrate 11is provided with a plurality of conductive pads each constituting onepixel of the display. Each conductive pad are formed together with ann-channel FET 51 whose source is electrically connected with thecorresponding pad. The drains of the FETs on a similar row in the matrixis connected with a control line of the row to which control signals aresupplied from a row driver 47. The gates of the n-channel FETs on asimilar column are connected with a control line of the column to whichcontrol signals are supplied from a column driver 46.

In the operation of the display, the column driver 46 supplies controlsignals of a high level to selected columns to turn on the TFTs on thecolumn. There are, however, undesirable cases in which the on-off actionof the TFTs can not sufficiently carry out so that the output voltage ofthe TFT (i.e. the input to the pixel) reaches only short of apredetermined high voltage level (e.g. 5 V), or the output voltage doesnot sufficiently fall to a predetermined low voltage (e.g. 0 V). This isbecause of the asymmetrical characteristics of the TFTs. Namely, thecharging action on the liquid crystal layer takes place in a dissimilarmanner as the discharging action therefrom. Furthermore, since theliquid crystal is intrinsically insulating, the liquid crystal voltage(V_(LC)) becomes floating when the TFT is turned off. The amount ofelectric charge accumulated on the liquid crystal which is equivalent toa capacitance determines the V_(LC). The accumulated charge, however,will leak through a channel resistance R_(SD) which may be formed bydust or ionized impurities or through the liquid crystal itself whoseresistance R_(LC) 44 may be occasionally decreased. For this reason,V_(LC) sometimes becomes at an indeterminate intermediate voltage level.In the case of the panel having two hundred thousands to 5 millionpixels, a high yield call not be expected in such a situation.

Also, in the conventional driving methods, the liquid crystal materialto which control voltages are applied is subjected to an averageelectric field in one direction during operation. The electric fieldtends to cause electrolysis when continuously used. Because of this, theaging of the liquid crystal material is accelerated and the life time ofthe display is decreased.

Furthermore, it has been difficult to realize grey tone display, withoutcomplicated structure, capable of arbitrarily displaying a variety ofvisual images in various shade of grey.

BRIEF SUMMARY OF THE INVENTION

It is an object of the present invention to provide a grey tone displayand a driving method for the same capable of demonstrating clear visualimages.

It is another object of the present invention to provide a grey tonedisplay and a driving method for the same capable of accurate operation.

It is a further object of the present invention to provide a grey tonedisplay and a driving method for the same capable of arbitrarilydisplaying a variety of visual images in various shade of grey.

Additional objects, advantages and novel features of the presentinvention will be set forth in the description which follows, and inpart will become apparent to those skilled in the art upon examinationof the following or may be learned by practice of the present invention.The object and advantages of the invention may be realized and attainedby means of the instrumentalities and combinations particularly pointedout in the appended claims.

To achieve the foregoing and other object, and in accordance with thepresent invention, as embodied and broadly described herein, a displaycomprises a light influencing medium, electrode patterns defining aplurality of pixels in the medium and a control circuit for supplyingcontrol signals to the electrode patterns. The control circuit suppliesthe control signal to each pixel through a switching element whichcomprises at least one complimentary transistors connected between a lowlevel and a high level. By the use of the conplimentary transistors, thevoltage level of each pixel during its operation is prevented fromfluctuating.

Particularly, the complimentary transistors are coupled in series attheir source terminals to the output terminal of the complimentarytransistors. The input terminal of the complimentary transistors istheir gate terminals coupled to each other. By this construction, whenthe complimentary transistors are connected between a suitable highvoltage and a suitable low voltage, the output terminal of thecomplimentary transistors is brought to the input level at their gateterminals from which the threshold voltage is subtracted. Accodingly,the voltage applied to the light influencing voltage call be arbitrarilyadjusted by regulating the input level resulting in visual images invarious shade of grey. This is particularly fitted to light influencingmediums of dispersion type liquid crystals whose thresholds have certainwidths.

In typical driving methods, the display of this type is driven byapplying control signals in the form of pulses to conductive pads. Thelight influencing medium is disposed between the conductive pads and aback electrode. The back electrode is supplied with an alternate voltagein order to make zero the average voltage applied to the light influencemedium.

In typical example, the present invention is applied to liquid crystaldisplays. Each pixel of the display is provided with a switching elementof complimentary thin film field effect transistors which forcibly pullor push the level of the liquid crystal layer to a definite high or lowvoltage level rather than a floating state. Of course, the presentinvention call be practiced with a variety of other type transistors,other than thin film transistors, such as staggered types, coplannertypes, inverted staggered types, inverted coplanner types. The channelregions of the transistors may be spoiled by introduction of a suitalbeimpurity in order to eliminate the undesirable influence of incidentlight by reducing the photosensitivity of the transistors. When controltransistors of a driver for supplying control signals to the switchingtransistors are formed also on the same substrate at its peripheralposition where no light is incident, they are not spoiled by theimpurity. In such a case, two types of transistors are formed on thesubstrate, one being spoiled and the other not being spoiled and havinga carrier mobility 2 to 4 times larger than that of the spoiledtransistors.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and form a part ofthe invention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a schematic diagram showing an equivalent circuit of a liquidcrystal display.

FIG. 2 is a cross sectional schematic view showing an generalconfiguration of a liquid crystal display.

FIG. 3 is a schematic diagram showing an equivalent circuit of a liquidcrystal display in accordance with a first embodiment of the presentinvention.

FIGS. 4(A), 4(B) and 4(C) are plan and cross sectional views showing theliquid crystal display illustrated in FIG. 3

FIGS. 5(A) and 5(B) are explanatory views demonstrating operation of theliquid crystal display in accordance with the first embodiment.

FIG. 6 is a schematic view showing a system suitable for manufacturingthin film field effect semiconductor transistors in accordance with thepresent invention.

FIG. 7(A) is a schematic view showing a planar type magnetron RFsputtering apparatus of the system illustrated in FIG. 6 suitable foruse in depositing oxide and semiconductor films.

FIG. 7(B) is an explanatory view showing the arrangement of magnetsprovided in the apparatus as illustrated in FIG. 7(A).

FIGS. 8(A) to 8(F) are cross sectional views showing a method ofmanufacturing thin film field effect semiconductor transistors suitablefor the first embodiment of the present invention.

FIG. 9(A) is a schematic diagram showing an equivalent circuit of aliquid crystal display in accordance with a second embodiment of thepresent invention.

FIG. 9(B) is a plan sectional view showing the liquid crystal displayillustrated in FIG. 9(A).

FIG. 10(A) is a schematic diagram showing an equivalent circuit of aliquid crystal display in accordance with a third embodiment of thepresent invention.

FIG. 10(B) is a plain sectional view showing the liquid crystal displayillustrated in FIG. 10(A).

FIG. 11 is a schematic diagram showing an equivalent circuit of a liquidcrystal display in accordance with a fourth embodiment of the presentinvention.

FIG. 12 is an explanatory diagram demonstrating operation of thecomplimentary transistors of the liquid crystal display in accordancewith the fourth embodiment.

FIG. 13 is a chlonological diagram demonstrating operation of the liquidcrystal display in accordance with the fourth embodiment.

FIG. 14 is a schematic diagram showing an equivalent circuit of a liquidcrystal display corresponding to FIG. 13 in accordance with the fourthembodiment of the present invention.

FIG. 15 is a schematic diagram showing an equivalent circuit of a liquidcrystal display in accordance with a fifth embodiment of the presentinvention.

FIG. 16 is a chlorological diagram demonstrating operation of the liquidcrystal display in accordance with the fifth embodiment.

FIG. 17 is a schematic diagram showing an equivalent circuit of a liquidcrystal display in accordance with a sixth embodiment of the presentinvention.

FIG. 18 is a chlonological diagram demonstrating operation of the liquidcrystal display in accordance with the sixth embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 3 is a diagram illustrating the equivalent circuit of a liquidcrystal display in accordance with a first embodiment of the presentinvention. The diagram shows only a 2×2 matrix for the sake ofconvenience in description whereas ordinary liquid crystal displaysconsist of more great numbers of pixels such as a 640×480 matrix, a1260×960 matrix. The liquid crystal display includes a liquid crystallayer 42 disposed between a pair of glass substrates 11 and 11' as shownin FIG. 2. The inner surface of the glass substrate 11' is coated withan electrode 53. The inner surface of the other substrate 11 is providedwith a plurality of conductive pads 37b each constituting one pixel ofthe display as seen from FIG. 4(A). Dashed line is enclosing one pixelin the figure. Each conductive pad 37b are formed on the substratetogether with CMOS transistors consisting of an n-channel FET 51 and ap-channel FET 41 whose sources 34b' and 34b are electrically connectedwith the corresponding pad 37b. The drains of the n-channel FETs of theCMOSs on a similar row is connected with a V_(DD) line 48 of the row.The drains of the p-channel FETs of the CMOSs on a similar row isconnected with a Vss line 49 of the row. The gates of the p-channel andn-channel FETs of the CMOSs on a similar column is connected with aV_(CC) line of the column. The Vss lines and the V_(DD) lines areconnected with a row driver 47 and supplied with control signaltherefrom. The V_(CC) lines 52 are connected with a column driver 46 andsupplied with control signal therefrom. The column driver 46 and the rowdriver 47 are formed on the projected end of the glass substrate 11 aswill be understood form the illustration of FIG. 2.

When a TN liquid crystal material is used, the distance of thesubstrates is selected to be about 10 μm and both the inner surfaces ofthe substrates are provided with orientation control films which aregiven suitable rubbing treatment. When a ferroelectric liquid crystal(FLC) material is used, the distance of the substrates is selected to beabout 1.5 to 3.5 μm, e.g. 2.3 μm and only one of the inner surfaces (thesurface of the ground electrode) is provided with an orientation controlfilm given suitable rubbing treatment. The driving voltage is '20 V.When a liquid crystal material of dispersion type or a polymer liquidcrystal material is used, the distance of the substrates is selected tobe about 1.0 to 10.0 μm, e.g. 2.3 μm and no orientation control film isnecessary. The driving voltage is '10 to '15 V. In this case,polarization plates are also unnecessary and therefore the amount ofavailable light call be relatively increased in either type oftransmission and reflective types. Accordingly, whereas the liquidcrystal layer possesses no threshold voltage, a large contrast indisplayed images is realized and undesirable cross-talk is effectivelyprevented by the use of complimentary TFTs which provide a definitethreshold voltage.

The operation of the complimentary transistors will be explained withreference to FIGS. 5(A) and 5(B). Let the V_(DD) line and the Vss linebe in +10 V and -10 V respectively. The n-channel transistor 51 is tunedon and the p-channel transistor 41 turned off when a positive voltageV_(CC) is applied to the gate terminals 40 and 40' as illustrated inFIG. 5(A). This condition continues until the source voltage levelreaches V_(CC) -Vth. Namely, the n-channel transistor is turned off whenthe effective gate voltage (the gate voltage relative to the sourcevoltage) comes short of the threshold voltage Vth. Of course, then-channel transistor always supplies electric charge to the sourceterminal in order to maintain the source voltage level at that levelcoping with current leakage from the source terminal. Accordingly, thesource terminal, i.e. the output level of the complimentary transistorsis fixed to the V_(CC) -Vth level so that the output level can becontrolled by the input gate signal.

Contrary to this, the n-channel transistor 51 is tuned off and thep-channel transistor 41 turned on when a negative voltage V_(CC) isapplied to the gate terminals 40 and 40' as illustrated in FIG. 5(B).This condition continues until the source voltage level falls to V_(CC)-Vth. Namely, the p-channel transistor is turned off when the effectivegate voltage (the gate voltage relative to the source voltage) comesbeyond the threshold voltage -Vth. Of course, the n-channel transistoralways discharges the source terminal in order to maintain the sourcevoltage level at that level coping with current leakage from the sourceterminal. Accordingly, the source terminal, i.e. the output level of thecomplimentary transistors is fixed to the V_(CC) -Vth level so that theoutput level can be controlled by the input gate signal also in thiscase.

Referring now to FIG. 6, FIGS. 7(A) and 7(B) and FIGS. 8(A) to 8(F), amethod of manufacturing gate insulated field effect transistors 41 and51 constituting a CMOS in accordance with a first embodiment of thepresent invention will be explained. FIG. 6 is a schematic view showingmulti-chamber sputtering system for depositing semiconductor and oxidefilms by magnetron RF sputtering. The system comprising a loading andunloading pre-chamber 1 provided with a gate valve 5, a subsidiarychamber 2 connected to the pre-chamber 1 through a valve 6 and first andsecond individual sputtering apparatuses 3 and 4 connected to thesubsidiary chamber 2 respectively through valves 7 and 8. Thepre-chamber 1 is provided with an evacuation system 9 comprising arotary pump and a turbo molecular pump in series. The subsidiary chamber2 is provided with a first evacuation system 10a for roughing comprisinga rotary pump and a turbo molecular pump in series, a second evacuationsystem 10b for high vacuum evacuation comprising a cryosorption pump anda heater 10c located in the chamber 2 in order to heat substrates to becoated. If substrates to be coated are thermally contracted in advanceby heating in the subsidiary chamber 2, thermal contraction and stresscaused in films during deposition thereof on the substrate is reduced sothat the adhesivity of the films can be improved.

The sputtering apparatuses 3 and 4 are individual planar type magnetronRF sputtering apparatuses suitable for exclusive use in depositing oxidefilms and semiconductor films respectively when used in accordance withthe present invention. FIGS. 7(A) and 7(B) illustrate details of the RFsputtering apparatus. The apparatus comprises a vacuum chamber 20, afirst evacuation system 12-1 for roughing consisting of a turbomolecular pump 12b and a rotary pump 12d respectively provided withvalves 12a and 12c, a second evacuation system 12-2 for high vacuumevacuation comprising a cryosorption pump 12e provided with a valve 12f,a metallic holder 13 fixed in the lower side of the chamber 20 forsupporting a target 14 thereof, formed with inner conduit 13a throughwhich a coolant can flow to cool the target 14 and provided with anumber of magnets 13b such as parmament magnets, an energy supply 15consisting of an RF (e.g. 13.56 MHz) source 15a provided with a matchingbox 15b for supplying RF energy to the holder 13, a substrate holder 16located in the upper position of the chamber 20 for supporting asubstrate 11 to be coated, a heater 16a embedded in the substrate holder16, a shutter 17 intervening the substrate 11 and the target 14 and agas feeding system 18. Numeral 19 designates sealing means for ensuringair-tight structure of the vacuum chamber 20. In advance of actualdeposition on the substrate 11, impurities occurring in the targets aresputtered and deposited on the shutter 17 intervening the substrate 11and the target 14, and then the shutter is removed in order to enablenormal deposition on the substrate 11. The magnets 13b are oriented tohave their N poles at the upper ends and S poles at the lower ends andhorizontally arranged in a circle as illustrated in FIG. 7(B) in orderto confine electrons in a sputtering region between the substrate 11 andthe target 14.

Referring now to FIGS. 8(A) to 8(F) together with FIG. 6 and FIGS. 7(A)and 7(B), a method of manufacturing thin film field effect transistors41 and 51 in accordance with the first preferred embodiment of theinvention will be described in details. This exemplary method is carriedout with a multi-chamber apparatus suitable for mass-production. Thisis, however, applicable to similar processes utilizing separate chamberswithout substantial modification.

10 sheets of glass substrate are mounted on a cassette and placed in theloading and unloading pre-chamber 1 through the valve 5. The substratesmay be made from an inexpensive glass which can endure thermal treatmentat high temperatures up to 700° C., e.g. about 600° C. such as NO glassmanufactured by Nippon Electric Glass Co. Ltd., LE-30 glass manufacturedby Hoya Co. or VYCOR glass manufactured by Corning Corp. After adjustingthe inner conditions of the pre-chamber 1 and the subsidiary chamber 2to each other, the cassette is transported from the pre-chamber 1 intothe subsidiary chamber 2 through the valve 6. One of the glasssubstrates is disposed in the first magnetron RF sputtering apparatus asshown in FIG. 7(A) by means of a transportation mechanism (not shown)and coated with a SiO₂ film 32 as a blocking film to a thickness of 1000Å to 3000 Å in a 100% O₂ atmosphere (0.5 Pa) at a substrate temperatureof 150° C. The output power of the apparatus is 400 W to 800 W in termsof 13.56 MHz RF energy. A single crystalline silicon or a quartz blockis used as a target. The deposition speed is 30 to 100 Å/mim. The coatedsubstrate is then exchanged by another of the remaining 9 substratewhich is subsequently coated with a SiO₂ film in the same manner. Allthe substrates mounted on the cassette are coated with a SiO₂ film byrepeating this procedure. During this procedure, the transportation of asubstrate between the pre-chamber 1 and the subsidiary chamber 2 has tobe carried out after adjusting the pressures and the inner atmospheresof the chambers 1 and 2 to each other in order to eliminate undesirableimpurities.

An amorphous silicon film 33 is next deposited in the second sputteringapparatus 4 on the SiO₂ film 32 to a thickness of 500 nm to 1 μm, e.g.2000 Å. The total density of oxygen, carbon and nitrogen in theamorphous film is preferably between 5×10²⁰ to 5×10²¹ cm⁻³ in order toeliminate undesirable influence of incident light on the channel regionof the transistor by reducing photosensitivity. The photosensitivity ofthe channel can be alternatively reduced by introducing an spoilingimpurity selectively into the channel. In this case, the total densityof oxygen, carbon and nitrogen in the amorphous film does desirably notexceed 7×10²⁰ cm³ , preferably not to exceed 1×10¹⁹ cm³. Such lowdensity makes it easy to recrystallize the source and the drain to beformed in the silicon film in the latter step by thermal treatment. Forthe formation of the silicon film 33, the 10 substrates are placed intothe apparatus 4 one after another from the subsidiary chamber 2 in thesame manner and treated therein for deposition of the amorphous siliconfilm. The transportation each substrate between the apparatus 4 and thesubsidiary chamber 2 is carried out after adjusting the pressures andthe inner atmospheres of the chambers 2 and 4 in order to eliminateundesirable impurities. This procedure is generally employed when it isdesired to transport the substrates between the first or secondsputtering apparatus and the subsidiary chamber, even if notparticularly described hereinbelow. The atmosphere in the apparatus 4comprises a mixture consisting of hydrogen and argon so that H₂ /(H₂+Ar)=0.8 (0.2 to 0.8 in general) in terms of partial pressure. Thehydrogen and argon gases have desirably purities of 99.999% and 99.99%respectively and are introduced after the inside of the apparatus 4 isevacuated to a pressure not higher than 1×10⁵ Pa. The total pressure is0.5 Pa: the output power of the apparatus is 400 W to 800 W in terms of13.56 MHz RF energy: a single crystalline silicon desirably containingoxygen atoms at a concentration of no higher than 5×10 ^(n) cm³, e.g1×10¹¹ cm³ is used as a target: and the substrate temperature ismaintained at 150° C. (deposition temperature) by the heater 16a in thesame manner. In preferred embodiments, the hydrogen proportion in themixture may be chosen between 5% and 100%; the deposition temperaturebetween 50° C. and 500° C., e.g. 150° C.; the output power between 1 Wand 10 MW in a frequency range from 500 Hz to 100 GHz which may becombined with another pulse energy source.

Alternatively, the amorphous silicon film 33 may be deposited by lowpressure CVD (LPCVD) or plasma CVD. In the case of LPCVD, the depositionis carried out by introducing disilane (Si₂ H₆) or trisilane (Si₃ H₈) ina suitable CVD chamber. The deposition temperature is selected at atemperature 100° C. to 200° C. lower than the recrystallizationtemperature of the silicon, i.e. 450° C. to 550° C., for example 530° C.The deposition speed is 50 to 200 Å/min. Boron may be introduced at1×10¹⁵ cm³ to 1×10¹⁸ cm³ into the film by using diboran as a dopant gastogether with the silane in order to make even the threshold voltages ofN-type and P-type TFTs. In the case of plasma CVD, the deposition iscarried out by introducing monosilane (SiH₄) or disilane (Si₂ H₆) at300° C. in a suitable plasma CVD chamber. The input energy is forexample high frequency electric energy at 13.56 MHz.

The oxygen density of the semiconductor film are preferably no higherthan 5×10²¹ cm⁻³ because if the oxygen density is too high, thermaltreatment have to be carried out at a high temperature for a long timein order to sufficiently recrystallize the semiconductor film in alatter step. The oxygen density, however, must not be too low becauseleak current in the off condition of the TFT increases in response to aback light which may be provided in the liquid crystal display ifparticular spoiling impurity is not used. For this reason, the oxygendensity is selected between 4×10¹² to 4×10²¹ cm⁻³. In accordance withexperiments, it was confirmed by SIMS (secondary ion mess spectroscopyanalysis) that hydrogen was involved at densities of 4×10²⁰ cm³equivalent to one atom % assuming the density of silicon being 4×10²²cm³. These figures of density were minimum values of the respectiveelements which varied along the depth direction. The reason why suchminimum values were employed is that a natural oxide existed at thesurface of the semiconductor film. If it is desired to spoil the channelregion, oxygen may be introduced as a spoiling agent to a portion of thesemiconductor film to be a channel region to a density of 5×10²⁰ to5×10²¹ cm⁻³ after deposition of the semiconductor film. In this case,the deposition of the semiconductor film can be carried out in orderthat the total density of oxygen in the semiconductor film does notexceed 7×10²⁰ cm³, preferably not to exceed 1×10¹⁹ cm⁻³. Such lowdensity makes it easy to recrystallize the source and drain regions ofthe semiconductor film in the latter step by thermal treatment. In thiscase, when TFTs for peripheral circuits located not to be exposed toillumination are formed in the same time, the mobility of the TFTs canbe increased, because the oxygen introduction is prevented, resulting ina high speed operation.

After all the substrates are coated with the silicon oxide and amorphoussilicon semiconductor films, thermal treatment is given thereto in thesubsidiary chamber 2 by means of the heater 10 c at 450° C. to 700° C.typically at 600° C., for 12 to 70 hours in a non-oxidizing atmosphere,e.g. in hydrogen. The film is recrystallized by this treatment (thermalannealing) in the form of semi-amorphous or semi-crystalline structure.

Next, the mechanism of formation of semi-amorphous or semi-crystallinesemiconductor material in accordance with the present invention will beexplained. When sputtering a single crystalline silicon target in amixture of hydrogen and argon, high energy heavy argon atoms collidewith the surface of the target, dislodge therefrom clusters eachconsisting of several tens to several hundred thousands of siliconatoms, and deposit the clusters on a substrate to be coated. Theseclusters pass through the mixture gas in advance of the deposition onthe substrate and are coupled with hydrogen atoms at their externalsurfaces in order to terminate their dangling bonds. Accordingly, whendeposited on the substrate, the clusters comprise internal amorphoussilicon and external ordered silicon including Si--H bonds The Si--Hbonds react with other Si--H bonds and are converted to Si--Si bonds bythermal treatment at 450° C. to 700° C. in a non-oxidizing atmosphere.These coupling of adjacent silicon atoms (Si--Si) function to letadjacent clusters be attracted to each other whereas these clusters havea tendency to convert their phases to more ordered phases (partialrecrystallization). As a result, the crystalline structure of theseclusters is given lattice distortion and the peak of its Raman spectra(522 cm¹ : the peak of single crystalline silicon) is displaced to thelow frequency direction. The apparent grain diameter calculated based onthe half-width is 50 to 500 Å which seems to indicate microcrystals.

The energy bands of the clusters are connected through the Si--Si bondsanchoring the clusters at the interfaces therebetween. For this reason,the polycrystalline (semi-amorphous or semi-crystalline) structure ofsilicon in accordance with the present invention is entirely differentthan usual polycrystals in which grain boundaries provide barriersagainst carrier transportation, so that the carrier mobility can be onthe order of 15 to 300 cm² /Vsec (electron mobility) and 10 to 200 cm²/Vsec (hole mobility). Namely, the semi-amorphous or semi-crystallinestructure in accordance with the present invention can be consideredsubstantially not to include undesirable grain boundaries. Of course, ifthe semiconductor is subjected to high temperatures of 1000° C. orhigher rather than the relatively low temperatures of 450° C. to 700°C., latent oxygen atoms come to appear at the boundaries between theclusters and form barriers like the prior art technique. The carriermobility can be improved by increasing the strength of the anchoring.For this purpose, the oxygen density in the semiconductor film isdecreased to 7×10¹⁹ cm³, desirably to 1×10¹⁹ cm³.

The amorphous silicon semiconductor film 33 is patterned by means of aphotomask as indicated by 1 to leave areas 33 and 33' which arenecessary to form N-channel and P-channel transistors. After all thesubstrates are coated with the silicon oxide and amorphous siliconsemiconductor films and patterned as described above, the substrates areplaced again in the first sputtering apparatus 3. The entire structureis then coated with a silicon oxide film 35 of a thickness of 500 Å to2000 Å, e.g. 1000 Å by sputtering in an oxide atmosphere as illustratedin FIG. 8(B). The deposition condition is same as that of the siliconoxide film 32 explained above. The characteristics at the interfacebetween the silicon oxide film 35 and the underlying semiconductor film33 can be improved by applying ultraviolet rays to carry out ozoneoxidation. Namely, the interface states can be decreased by utilizingphoto-CVD in combination with the sputtering explained in thedescription of deposition of the oxide film 32. Alternatively, fluorinemay be introduced in this deposition in order to fix sodium ions. Inthis case, the atmosphere comprises a high density oxygen (95%)including NF₃ (5%) at a total pressure of 0.5 Pa: the output power ofthe apparatus is 400 W in terms of 13.56 MHz RF energy: a singlecrystalline silicon or an artificial quartz is used as a target: and thesubstrate temperature is maintained at 100° C. By this procedure, thesilicon oxide film 35 to be a gate insulating film includes fluorineatoms which function to terminate dangling bonds of silicon atoms sothat the formation of fixed charge can be prevented at the interfacebetween the semiconductor films 33 and 33' and the oxide film 35. On thesilicon oxide film 35 is deposited by low pressure CVD a siliconsemiconductor film of 0.2 μm thickness which is highly doped withphosphorus at 1×10²¹ to 5×10²¹ cm³ followed, if desired, by coating aconductive film of 0.3 μm thickness made of molybdenum, tungsten film ora multiple film consisting of it and a MoSiO₂ or WSiO₂ film. Thesemiconductor film coated with the conductive (multiple) film is thenpatterned by photolithography with a suitable mask 2 in order to formgate electrodes 40 and 40'.

A photoresist film 27' is formed by the use of a photomask 3 in order tocover the semiconductor film 33'. With the gate electrode 40 and thephotoresist film 27', self-aligned impurity regions, i.e. a source and adrain region 34a and 34b are formed by ion implantation of boron at1×10¹⁵ cm² to 5×10¹⁵ cm². The intermediate region 28 of the siliconsemiconductor film 33 between the impurity regions 34a and 34b is thendefined as a channel region as illustrated in FIG. 8(C). After removingthe photoresist film 27', another photoresist film 27 is formed by theuse of a photomask 4 in order to cover the semiconductor film 33. Withthe gate electrode 40' and the photoresist film 27', self-alignedimpurity regions, i.e. a source and a drain region 34b' and 34a' areformed by ion implantation of phosphorus at 1×10¹⁵ cm² to 5×10¹⁵ cm².The intermediate region 28' of the silicon semiconductor film 33 betweenthe impurity regions 34a' and 34b' is then defined as a channel regionas illustrated in FIG. 8(D). The channel lengths of the p-channel andn-channel transistor are 10 μm respectively. The channel widths of thep-channel and n-channel transistor are 20 μm respectively. The ionimplantation may instead be carried out by selectively removing thesilicon oxide film 35 by the use of the gate electrode 40 or 40' as amask followed by direct ion implantation of boron or phosphorus.

After removing photoresist 27, the channel regions are then thermallyannealed at 600° C. for 10 to 50 hours in H₂ atmosphere to make activethe impurities in the drains and source regions. An interlayerinsulating film 37 of silicon oxide is deposited to a thickness of 0.2to 0.6 μm by the same sputtering method as described above over theentire surface of the structure followed by etching by means of aphotomask 5 for opening contact holes 39 through the interlayer film 37and the oxide film 35 in order to provide accesses to the underlyingsource and drain regions 34b, 34a, 34b' and 34a'. The deposition of theinterlayer insulating film 37 may be carried out by LPCVD, photo-CVD,ordinal pressure CVD (TEOS-ozone). Next, an aluminum film of 0.5 to 1 μmthickness is deposited on the structure over the contact holes 39 andpatterned to form source and drain electrodes 36b, 36a, 36b' and 36a' bymeans of a photomask 6 as illustrated in FIG. 8(F). An organic resinfilm 39 such as a transparent polyimide film is coated over thestructure to provide a planar surface and patterned by means of aphotomask 7 to provide accesses to the source electrodes 36b and 36b'followed by formation of lead electrode 37 made of a transparentconductive material such as indium tin oxide (ITO) to be electricallyconnected with the pad 37b. The ITO film is deposited by sputtering atroom temperature to 150° C. followed by annealing in an oxidizingatmosphere (O₂) or in air at 200 to 400° C. The pad 37b can be formed atthe same time by the deposition of the lead electrode 37. Then, theformation of CMOS transistors is finished. The mobility, the thresholdvoltage of the p-channel TFT are 20 cm² /Vs and -5.9 V. The mobility,the threshold voltage of the n-channel TFT are 40 cm² /Vs and 5.0 V. Theglass substrate thus provided with these CMOS transistors and suitableconductive patterns as illustrated is joined with a counterpart glasssubstrate provided with a ground electrode at its entire inner surfacefollowed by injection of a liquid crystal material between the twosubstrates. One of the advantages of the above process is that theformation of these transistors (spoiled and not spoiled) can be carriedout at temperatures no higher than 700° C. so that the process does notrequire the use of expensive substrates such as quartz substrates andtherefore suitable for large scale liquid crystal displays productionmethods.

In the above embodiment, thermal annealing is carried out twice at thesteps corresponding to FIGS. 8(A) and 8(D). The first annealing (FIG.8(A)), however, can be omitted to shorten the process time in the lightof the second annealing.

Referring to FIGS. 9(A) and 9(B), CMOS thin film field effecttransistors in accordance with a second preferred embodiment of thepresent invention will be illustrated. In this embodiment, two couplesof CMOS transistors 51-1, 41-1, 51-2 and 51-2 are connected in parallelto the conductive pad 37b for each pixel (as enclosed by dashed line) attheir source electrodes. These CMOS transistors are manufactured in thesteps explained above in conjunction with the first embodiment exceptthat the number of the transistors is doubled. The similar elements aregiven similar numerals as in the first embodiment. The electrode pads37b have to be deposited on the V_(CC) line through a suitableinsulating film therebetween. The electrical operation is substantiallysame as that of the first embodiment. Accordingly, two identicalindividual switching elements are prepared corresponding to one pixel sothat when the operation of one of them is fault, the ability ofinformation display can be maintained by firing the fault element bylaser rays in virtue of the remaining CMOS transistors. For this reason,the conductive transparent pads are formed in order not to cover theseTFTs.

Referring to FIGS. 10(A) and 10(B), CMOS thin film field effecttransistors in accordance with a third preferred embodiment of thepresent invention will be illustrated. Also in this embodiment, twocouples of CMOS transistors 51-1, 41-1 and 51-2 and 41-2 are connectedin parallel to an electrode pad 37b for each pixel at their sourceelectrodes. The electrode pad 37b, however, is separated into twoportions 37b-1 and 37b-2 each independently connected to a correspondingone of the two CMOS transistors. These CMOS transistors are manufacturedin the steps explained above in conjunction with the first embodimentexcept for the number of the transistors. The similar elements are givensimilar numerals as in the first embodiment. Then, each pixel comprisestwo individual sub-pixels. In accordance with this embodiment, even ifthe operation of one of the sub-pixels is fault, the other sub-pixel cansupport the operation of the pixel and therefore the deterioration ofgrey scales is substantially decreased.

As described above, there are following advantages in accordance withthe above embodiments of the present invention:

1) Visual images can be constructed in a variety of grey shade.

2) The voltage across the liquid crystal layer is stably fixed atdeterminate level in accordance with the output signal from thecomplimentary transistors rather than in an indeterminate floatingcondition.

3) Margins for operational fluctuation are broadened.

4) Even if some TFTs are fault, the operation thereof is followed up tosame extent.

5) The increase of the number of photomasks due to the employment ofcomplimentary transistors is only two (photomask 3 and 4) as comparedwith conventional cases utilizing only n-channel TFTs.

6) Since semi-amorphous or semi-crystalline semiconductors are used inplace of amorphous semiconductors and the carrier mobility is increasedby a factor of ten or more, the size of the TFT is substantially reducedso that little decrease of the aperture ratio is necessary even when twoTFTs are formed in one pixel.

FIG. 11 is a diagram illustrating the equivalent circuit of a liquidcrystal display in accordance with a fourth embodiment of the presentinvention. The pixel configuration as shown in FIG. 4 can be appliedalso for this embodiment. The diagram shows only a 2×2 matrix for thesake of convenience in description whereas ordinary liquid crystaldisplays consist of more great numbers of pixels such as a 640×480matrix, a 1260×960 matrix. The liquid crystal display includes a liquidcrystal layer 42 disposed between a pair of glass substrates 11 and 11'in the same manner as the first embodiment as shown in FIG. 2. Theentirety of the inner surface of the glass substrate 11' is coated witha back electrode 53. In this embodiment, however, the electrode 53 isnot ground but supplied with an offset voltage in accordance with thedriving mechanism of the liquid crystal display as detailedly explainedinfra. The inner surface of the other substrate 11 is provided with aplurality of conductive pads 37b each constituting one pixel of thedisplay in the same manner as the first embodiment. Each conductive pad37b are formed on the substrate together with CMOS transistorsconsisting of an N-type FET 51 and a P-type FET 41 whose sources 34b'and 34b are electrically connected with the corresponding pad 37b. Thedrains of the N-type FETs of the CMOSs on a similar row are connectedwith a V_(DD) line 48 of the row. The drains of the P-type FETs of theCMOSs on a similar row is connected with a Vss line 49 of the row. Thegates of the P-type and N-type FETs of the CMOSs on a similar column isconnected with a V_(CC) line of the column. The Vss lines and the V_(DD)lines are connected with a row driver 47 and supplied with controlsignal therefrom. The V_(CC) lines 52 are connected with a column driver46 and supplied with control signal therefrom.

FIG. 12 illustrates operational action of each pixel in response toseveral control signals applied to the V_(DD) line, the V_(SS) line, theV_(CC) line and the back electrode. When a positive voltage is appliedto the V_(DD) line and a negative voltage to the V_(SS) line, the liquidcrystal voltage level at the pixel (i.e. the voltage level of the pad37b) follows the voltage level at the V_(CC) line and the liquid crystalvoltage level is forcibly at ground if the V_(DD) line and the Vss lineare commonly grounded. Accordingly, the voltage applied between theliquid crystal at the pixel is calculated by subtracting the offset(bias) voltage applied to the back electrode from the liquid crystalvoltage.

The representative example of the driving method in accordance with thefourth embodiment of the present invention will be explained withreference to FIGS. 13 and 14. In FIG. 14, the 2×2 matrix of FIG. 11 isexpanded to a 4×4 matrix. The configurations of them, however, aresubstantially identical except the number of pixels. FIG. 13 illustratesthe control signals applied to the V_(DD) lines, the V_(SS) lines, theV_(CC) lines and the back electrode. The V_(DD) lines are called X_(1a),X_(2a), X_(3a) and X_(4a) from the first row to the forth row in thediagram whereas the Vss lines are called X_(1b), X_(2b), X_(3b) andX_(4b) in the same manner. The signals applied to the Vss lines areexactly the inversion of the signals to the V_(DD) line and thereforethe waveforms of the Vss lines are dispensed with in the illustration.The V_(CC) lines are called Y₁, Y₂, Y₃ and Y₄ from the left column tothe right column. In this driving method, the control signals applied tothe V_(DD) and Vss lines are addressing signals which scan from thefirst row to the forth row as shown in FIG. 13. Opposed pulses areapplied to the V_(DD) and Vss lines connected to one addressed row forthe time width of one fourth of the frame during which all the rows aresequentially scanned. The control signals applied to the V_(CC) linesare data signals which determine the visual pattern appearing on thedisplay.

If a pixel on the i-th row and the j-th column is desired to beactuated, a positive pulse is applied to the V_(CC) line of the j-thcolumn at the time when the i-th row is addressed by applying opposedpulses to the VDD and Vss lines on the i-th row. In FIG. 13, the pixelon the first column and the first row (given symbol AA in FIG. 14) isactuated in the first fourth of the first frame between T₁ and T₂, thesecond frame between T₂ and T₃ and the fifth frame between T₅ and T₆.The back electrode is biassed by a negative voltage between T₁ and T₆.The V_(DD), Vss and V_(CC) signal levels and the bias voltage are forexample 20 V, -20 V. '20 V and ¹ 10 V respectively in the case that theoptical characteristic of the liquid crystal is changed by the thresholdvoltage of 20 V thereacross. Accordingly, as understood from FIG. 12,such a high voltage as 30 V is applied only to the selected pixel (theAA pixel in the figure) while the voltage level applied to the otherpixel can not exceed 10 V. In T₆ to T₈ in FIG. 13, the voltage levels atthe V_(CC) lines and the back electrode are inversed so that the sign ofthe applied voltage on each pixel is simply inversed. Accordingly, sucha low voltage as -30 V is applied only to the selected pixel (the AApixel in the figure) while the absolute voltage level applied to theother pixel can not exceed 10 V. The pixel on the first column and thefirst row is actuated in the sixth frame between T.sub.₆ and T₇. Theinversion of the signs takes place repeatedly once per several frames toseveral tens of frames so that the average voltage applied to the liquidcrystal approaches to zero throughout the operation resulting ineffective prevention of deterioration of the liquid crystal.

In accordance with this embodiment, the voltage level of control signalsapplied to the liquid crystal layer can be easily adjusted to thethreshold level of the liquid crystal layer only by adjusting the biasvoltage level applied to the back electrode. The employment of the biasvoltage makes it possible to cancel out the effect of the electric fieldimpressed on the liquid crystal by periodically chaning the polarity ofthe bias voltage, resulting in the prevention of electrolysis of theliquid crystal material.

Referring to FIGS. 15 and 16, a liquid crystal display and a method fordriving the display in accordance with a fifth preferred embodiment ofthe present invention will be illustrated. In this embodiment, twocouples of CMOS transistors 41-1, 51-1 and 41-2', 51-2' are connected inparallel to an electrode pad 33 for each pixel (as enclosed by dashedline) at their source electrodes. These CMOS transistors aremanufactured in the steps explained above in conjunction with the firstembodiment except that the number of the transistors is doubled. Thesimilar elements are given similar numerals as in the first embodiment.The electrical operation is substantially same as that of the thirdembodiment. Accordingly, two identical individual switching elements areprepared corresponding to one pixel so that when the operation of one ofthem is fault, the ability of information display can be maintained byfiring the fault element by laser rays in virtue of the remaining CMOStransistors. For this reason, the conductive transparent pads are formedin order not to cover these TFTs.

The representative example of the driving method in accordance with thethird embodiment of the present invention will be explained withreference to FIG. 16. In FIG. 16, explanation is made for the display asshown in FIG. 15 but expanded in a 4×4 matrix. The configuration,however, is substantially identical except the number of pixels. FIG. 16illustrates the control signals applied to the V_(DD) lines, the V_(SS)lines, the V_(CC) lines and the back electrode in the same manner as thesecond embodiment. In this driving method, the control signals appliedto the V_(CC) lines are addressing signals which repeatedly scan fromthe first row to the fourth row as shown in FIG. 16. A negative orpositive pulse is applied to the V_(CC) line connected to an addressedcolumn. The control opposite signals applied to the V_(DD) and Vss linesare data signals which determine the visual pattern appearing on thedisplay.

If a pixel on the i-th row and the j-th column is desired to beactuated, opposed pulses are applied to the V_(DD) and Vss lines of thei-th row at the time when the j-th column is addressed by applying apositive pulse to the V_(CC) line on the j-th column. In FIG. 16, thepixel on the first column and the first row is actuated in the firstframe between T₁ and T₂, the second frame between T₂ and T₃ and thefifth frame between T₅ and T₆. The back electrode is biassed by anegative voltage between T₁ and T₆. The V_(DD), Vss and V_(CC) signallevels and the bias voltage are for example 20 V, -20 V, '20 V and '10 Vrespectively in the case that the optical characteristic of the liquidcrystal is changed by the threshold voltage of 20 V. Accordingly, asunderstood from FIG. 12, such a high voltage as 30 V is applied only tothe selected pixel while the voltage level applied to the other pixelcan not exceed 10 V. In T₆ to T₈ in FIG. 16, the voltage levels at theV_(CC) lines and the back electrode are inversed so that the sign of theapplied voltage on each pixel is simply inversed. Accordingly, such alow voltage as -30 V is applied only to the selected pixel while theabsolute voltage level applied to the other pixel can not exceed 10 V.The pixel on the first column and the first row is actuated in the sixthframe between T₆ and T₇. The inversion of the signs takes placerepeatedly once per several frames to several tens of frames so that theaverage voltage applied to the liquid crystal approaches to zeroresulting in effective prevention of deterioration of the liquidcrystal.

Referring to FIGS. 17 and 18, a sixth preferred embodiment of thepresent invention will be illustrated. Also in this embodiment, twocouples of CMOS transistors 41-1, 51-1 and 41-2', 51-2' are connected inparallel to an electrode pad 37b for each pixel at their sourceelectrodes. The electrode pad 37b, however, is separated into twoportions 37b-1 and 37b-2 each independently connected to a correspondingone of the two CMOS transistors in the same manner as FIG. 10(B). TheseCMOS transistors are manufactured in the steps explained above inconjunction with the first embodiment except for the number of thetransistors. The similar elements are given similar numerals as in thefirst embodiment. Then, each pixel comprises two individual sub-pixels.In accordance with this embodiment, even if the operation of one of thesub-pixels is fault, the other sub-pixel can support the operation ofthe pixel and therefore the possibility of deterioration in grey scaleis substantially decreased. Also, even when the operational speed of onesub-pixel becomes low, the quality of the displayed image is not sodeteriorated.

The representative example of the driving method in accordance with thesixth embodiment of the present invention will be explained withreference to FIG. 18. In FIG. 18, explanation is made for the display asshown in FIG. 17 but expanded in a 4×4 matrix. The configuration,however, is substantially identical except the number of pixels. FIG. 18illustrates the control signals applied to the V_(DD) lines, the V_(SS)lines, the V_(CC) lines and the back electrode in the same manner as thefourth embodiment. In this driving method, the control signals appliedto the V_(DD) and Vss lines are addressing signals which scan from thefirst row to the forth row as shown in FIG. 18. Opposed pulses areapplied to the V_(DD) and Vss lines collected to an addressed row. Thecontrol signals applied to the V_(CC) lines are data signals whichdetermine the visual pattern appearing on the display. In thisembodiment, however, control signals applied to the V_(CC) lines arepositive or negative pulses whose pulse width is only one 16th of oneframe (e.g. between T₁ and T₂). The pulse width of addressing signalsapplied to the V_(DD) and Vss lines is on the other hand one fourth ofthe frame in the same manner as the second embodiment. The 16th divisionfashion is suitable for color displays.

If a pixel on the i-th row and the j-th column is desired to beactuated, a positive pulse is applied to the V_(CC) line of the j-thcolumn at the time when the i-th row is addressed by applying opposedpulses to the VDD and Vss lines on the i-th row. In FIG. 18, the pixelon the first column and the first row is actuated in the first framebetween T₁ and T₂. The back electrode is biassed by a negative voltagebetween T₁ and T₃. The V_(DD), Vss and V_(CC) signal levels and the biasvoltage are for example 20 V, -20 V, '20 V and '10 V respectively in thecase that the optical characteristic of the liquid crystal is changed bythe threshold voltage of 20 V in the same manner. Accordingly, asunderstood from FIG. 18, such a high voltage as 30 V is applied only tothe selected pixel while the voltage level applied to the other pixelcan not exceed 10 V. In T₃ to T₄ in FIG. 18, the voltage levels at theV_(CC) lines and the back electrode are inversed so that the sign of theapplied voltage on each pixel is simply inversed. Accordingly, such alow voltage as -30 V is applied only to the selected pixel while theabsolute voltage level applied to the other pixel can not exceed 10 V.The pixel on the first column and the first row is actuated in the thirdframe between T₃ and T₄. The inversion of the signs takes placerepeatedly once per several frames to several tens of frames so that theaverage voltage applied to the liquid crystal approaches to zeroresulting in effective prevention of deterioration of the liquidcrystal.

The foregoing description of preferred embodiments has been presentedfor purposes of illustration and description. It is not intended to beexhaustive or to limit the invention to the precise form described, andobviously many modifications and variations are possible in light of theabove teaching. The embodiment was chosen in order to explain mostclearly the principles of the invention and its practical applicationthereby to enable others in the art to utilize most effectively theinvention in various embodiments and with various modifications as aresuited to the particular use contemplated. Examples are as follows:

The above embodiments are applications in the form of CMOSs forswitching devices in liquid crystal displays. The TFT in accordance withthe present invention, however, can be utilized in the form of aswitching device comprising one TFT for driving one pixel. In this case,the equivalent circuit is substantially same as that illustrated in FIG.1 except that the resister R_(SD) is not effective because the N-typeTFT is constructed with a spoiled semiconductor film which is notsensitive to incident light as explained above. The electrode pad ofeach pixel becomes electrically floating when not addressed in thismodification so that the voltage level thereof may not be so fixed ascompared with those utilizing CMOSs. The manufacturing process thereof,however, is very simple without the need of light blocking means.

The liquid crystal material used in the liquid crystal display mayinclude other type materials. For example, a suitable phase transitionliquid crystal materials can be prepared by adding an ion dopant into anematic liquid crystal material of guest-host type or dielectricanisotropic type. The phase transition liquid crystal material changes,in accordance with application of an electric field, its opticalappearance from a transparent state to a cloudy state and vice versathrough phase transition between its nematic phase and its cholestericphase. Furthermore in place of liquid crystals, suitable lightinfluencing materials are also utilized in the same purpose such aselectrophoresis dispersions which are prepared by dispersing pigmentparticles in an organic liquid which has been colored by a dye. If greyscale is desired, a plurality of frames are given to one image to bedisplayed and selected pixels are actuated only in a fewer frames thanthe given frames in accordance with the desired grey tone.

The present invention can be applied to displays utilizing other typesof semiconductor devices such as germanium or silicon/germanium (Si₂Ge₇) semiconductor devices, in which case the thermal treatment can bedone at temperatures approx. 100° C. lower than those used for siliconsemiconductors in the above embodiments. The deposition of suchsemiconductor can be carried out by sputtering in a high energy hydrogenplasma caused by optical energy (shorter than 1000 nm wavelength) orelectron cyclotron resonance (ECR). Instead of gases including hydrogenmolecules, some hydrogen compounds can be used as the atmosphere ofsputtering as long as not to be impurity. For example, monosilane ordisilane may be used for forming silicon semiconductor transistors.Although in the preferred embodiments, oxide and semiconductor films aredeposited respectively in separate apparatuses, it is apparently alsopossible to deposit other types of gate insulating films or gateelectrodes in a common apparatus. During deposition of oxide films, ahalogen such as fluorine may be used as an atmosphere of sputtering soas to introduce halogen atoms into the oxide films in order toeffectively prevent alkali metal atoms from getting into the film fromthe glass substrate by virtue of neutralization. The same effect can beexpected by introduction of phosphorus in place of halogens.

The present invention can be applied for other types of optical devicesutilizing semiconductor devices such as image sensors, load elements orthree-dimensional elements of monolithic integrated semiconductordevices. In the preferred embodiments field effect transistors areformed on a glass substrate. However, other substrates can be usedinstead. For example, thin film field effect transistors may be formedon a silicon substrate in a liquid crystal display or an image sensordevice. This silicon substrate may be an intrinsic silicon substrate, ap-type silicon substrate, an n-type silicon substrate, or a siliconsubstrate in which MOSFETs, bipolar transistors, or the like areprovided in the form of IC. An insulating layer is provided between sucha substrate and the thin film field effect transistors although such aninsulating layer may be dispensed with in the case of the intrinsicsilicon substrate.

A gate electrode may be either a single layer electrode or a multi-layerelectrode in a gate insulated field effect transistor in accordance withthe present invention. The single layer gate electrode may be a siliconelectrode doped with phosphorus or an aluminum electrode. Themulti-layer gate electrode may be a two-layer electrode which consistsof a lower chromium layer and an upper aluminum layer formed thereon ora two-layer electrode which consists of a lower silicon layer doped withphosphorus and an upper metallic or metal silicide layer formed thereon.The aluminum single layer electrode and the upper aluminum layer can beformed by sputtering an aluminum target. The silicon single layerelectrode and the lower silicon layer can be formed by low pressure CVDor by sputtering a silicon target doped with phosphorus. The lowerchromium layer can be formed by sputtering a chromium target. Themetallic layer may be a molybdenum layer formed by sputtering amolybdenum target, a wolfram layer formed by sputtering a wolframtarget, a titanium layer formed by sputtering a titanium target, or analuminum layer formed by sputtering an aluminum target. The metalsilicide layer may be a MoSi₂ layer formed by sputtering a MoSi₂ target,a WSi₂ layer formed by sputtering a WSi₂ target, or a TiSi₂ layer formedby sputtering a TiSi₂ target. Although the production method claims asprovided infra include several steps, the order of these steps can bechanged in accordance with the practical cases and should not limit thescope of patent.

What is claimed is:
 1. An electro-optical liquid crystal devicecomprising:a first substrate having an insulating surface; a secondsubstrate opposing said first substrate; a liquid crystal materialbetween said first and second substrate: at least one thin filmtransistor formed on said insulating surface, said thin film transistorcomprising source, drain and channel regions; an interlayer insulatingfilm comprising an inorganic material formed on said thin filmtransistor; an organic resin film provided over said thin filmtransistor and said interlayer insulating film; and a pixel electrodeformed over said organic resin film and connected to said thin filmtransistor through an opening provided in said organic resin film forswitching said liquid crystal material, wherein said interlayerinsulating film is located between said organic resin film and saidchannel region of the thin film transistor, and wherein said thin filmtransistor comprises silicon crystals of which apparent grain diametercalculated based on half-width of Raman spectra is 50 to 500 Å.
 2. Anelectro-optical device according to claim 1 wherein said pixel electrodeis a transparent conductive film.
 3. An electro-optical device accordingto claim 1 wherein said pixel electrode is connected to said thin filmtransistor via said conductive film.
 4. An electro-optical deviceaccording to claim 1 wherein said inorganic material comprises siliconoxide.
 5. An electro-optical device according to claim 1 wherein saidchannel region comprises a material selected from the group consistingof silicon, germanium and a combination thereof.
 6. An electro-opticaldevice according to claim 1 wherein said gate insulating film is 500 Åto 2000 Å thick.
 7. An electro-optical device according to claim 1wherein said interlayer insulating film is 0.2 to 0.6 μm thick.
 8. Anelectro-optical device according to claim 1 consisting of 640×480 pixelsarranged in a matrix form.
 9. An electro-optical device according toclaim 1 consisting of 1260×960 pixels arranged in a matrix form.
 10. Anelectro-optical device according to claim 1 further comprising aconductive film formed on said interlayer film and electricallyconnected to said thin film transistor through a contact hole formed insaid interlayer insulating film.
 11. An electro-optical liquid crystaldevice comprising:a first substrate having an insulating surface; asecond substrate opposing said first substrate; a liquid crystalmaterial between said first and second substrate: at least one thin filmtransistor formed on said insulating surface, said thin film transistorcomprising source, drain and channel regions; an interlayer insulatingfilm comprising an inorganic material formed on said thin filmtransistor; an organic resin film provided over said thin filmtransistor and said interlayer insulating film; and a pixel electrodeformed over said organic resin film and connected to said thin filmtransistor through an opening provided in said organic resin film forswitching said liquid crystal material, wherein said interlayerinsulating film is located between said organic resin film and at leastsaid channel region of the thin film transistor, and wherein said thinfilm transistor comprises silicon and exhibits a peak of Raman spectra,displaced from 522 cm⁻¹.
 12. An electro-optical device according toclaim 11 wherein said pixel electrode is a transparent conductive film.13. An electro-optical device according to claim 11 wherein said pixelelectrode is connected to said thin film transistor via said conductivefilm.
 14. An electro-optical device according to claim 11 consisting of1260×960 pixels arranged in a matrix form.
 15. An electro-optical deviceaccording to claim 11 wherein said channel region comprises a materialselected from the group consisting of silicon, germanium and acombination thereof.
 16. An electro-optical device according to claim 11wherein said gate insulating film is 500 Å to 2000 Å thick.
 17. Anelectro-optical device according to claim 11 wherein said interlayerinsulating film is 0.2 to 0.6 μm thick.
 18. An electro-optical deviceaccording to claim 11 consisting of 640×480 pixels arranged in a matrixform.
 19. An electro-optical device according to claim 11 wherein saidinorganic material comprises silicon oxide.
 20. An electro-opticaldevice according to claim 11 further comprising a conductive film formedon said interlayer film and electrically connected to said thin filmtransistor through a contact hole formed in said interlayer insulatingfilm.
 21. An electro-optical liquid crystal device comprising:a firstsubstrate having an insulating surface; a second substrate opposing saidfirst substrate; a liquid crystal material between said first and secondsubstrate; at least one thin film transistor formed on said insulatingsurface, said thin film transistor comprising: a crystallinesemiconductor layer having source, drain and channel regions; a gateinsulating layer adjacent to said channel region; and a gate electrodeadjacent to said channel region; an interlayer insulating filmcomprising an inorganic material formed on said thin film transistor;and an organic resin film provided over said thin film transistor andsaid interlayer insulating film; wherein said interlayer insulating filmis located between said organic resin film and at least said channelregion of the thin film transistor, and wherein said semiconductor layercomprises silicon crystals of which apparent grain diameter calculatedbased on half-width of Raman spectra is 50 to 500 Å.
 22. Anelectro-optical device according to claim 21 further comprising a pixelelectrode formed over said organic resin film and connected to said thinfilm transistor through an opening provided in said organic resin film.23. An electro-optical device according to claim 22 wherein said pixelelectrode is a transparent conductive film.
 24. An electro-opticaldevice according to claim 21 wherein said inorganic material comprisessilicon oxide.
 25. An electro-optical device according to claim 21wherein said channel region comprises a material selected from the groupconsisting of silicon, germanium and a combination thereof.
 26. Anelectro-optical device according to claim 21 wherein said gateinsulating film is 500 Å to 2000 Å thick.
 27. An electro-optical deviceaccording to claim 21 wherein said interlayer insulating film is 0.2 to0.6 μm thick.
 28. An electro-optical device according to claim 21consisting of 640×480 pixels arranged in a matrix form.
 29. Anelectro-optical device according to claim 21 consisting of 1260×960pixels arranged in a matrix form.
 30. An electro-optical deviceaccording to claim 21 wherein said crystalline semiconductor layer hasan electron mobility from 15 to 300 cm² /Vsec.
 31. An electro-opticaldevice according to claim 21 wherein said crystalline semiconductorlayer has a hole mobility from 10 to 200 cm² /Vsec.
 32. Anelectro-optical liquid crystal device comprising:a first substratehaving an insulating surface; a second substrate opposing said firstsubstrate; a liquid crystal material between said first and secondsubstrate; at least one thin film transistor formed on said insulatingsurface, said thin film transistor comprising: a crystallinesemiconductor layer having source, drain and channel regions; a gateinsulating layer adjacent to said channel region; an interlayerinsulating film comprising an inorganic material formed on said thinfilm transistor; and an organic resin film provided over said thin filmtransistor and said interlayer insulating film; wherein said interlayerinsulating film is located between said organic resin film and at leastsaid channel region of the thin film transistor, and wherein saidsemiconductor layer comprises silicon and exhibits a peak of Ramanspectra, displaced from 522 cm⁻¹.
 33. An electro-optical deviceaccording to claim 32 further comprising a pixel electrode formed oversaid organic resin film and connected to said thin film transistorthrough an opening provided in said organic resin film.
 34. Anelectro-optical device according to claim 32 wherein said pixelelectrode is a transparent conductive film.
 35. An electro-opticaldevice according to claim 32 wherein said pixel electrode is connectedto said thin film transistor via said conductive film.
 36. Anelectro-optical device according to claim 32 wherein said inorganicmaterial comprises silicon oxide.
 37. An electro-optical deviceaccording to claim 32 wherein said channel region comprises a materialselected from the group consisting of silicon, germanium and acombination thereof.
 38. An electro-optical device according to claim 32wherein said gate insulating film is 500 Å to 2000 Å thick.
 39. Anelectro-optical device according to claim 32 wherein said interlayerinsulating film is 0.2 to 0.6 μm thick.
 40. An electro-optical deviceaccording to claim 32 consisting of 640×480 pixels arranged in a matrixform.
 41. An electro-optical device according to claim 32 consisting of1260×960 pixels arranged in a matrix form.
 42. An electro-optical deviceaccording to claim 32 wherein said crystalline semiconductor layer hasan electron mobility from 15 to 300 cm² /Vsec.
 43. An electro-opticaldevice according to claim 32 wherein said crystalline semiconductorlayer has a hole mobility from 10 to 200 cm² /Vsec.